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Software-Research

Master Thesis Student (f/m/d) - In-line Graph Decompression for FPGA-based Graph Processing

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ABOUT THE TEAM


The HANA Database Campus team organizes the work with students and the research activities within the HANA & Analytics teams.

 

THE ROLE


Context of the project
Field-programmable gate arrays (FPGAs) have been shown to excel at speeding-up graph algorithms (Yao, 2018). However, even highly optimized graph processing accelerators still suffer from a memory bottleneck (Dann, 2021). Thus, FPGA resources remain underutilized and allow implementing additional processing steps without negatively impacting performance of existing parts of the design.

 

Goal of the project
The goal of this thesis is to combine graph compression techniques (Brisaboa, 2009; Claude, 2010) with a FPGA-based graph processing accelerator to virtually increase the memory bandwidth. This means utilizing an in-line decompression step paired with a highly effective graph compression technique to alleviate the memory bottleneck.

 

Tasks for the student

  • Implement graph decompression sub-system on FPGA
  • Combine with our graph processing accelerator
  • Analyze performance and resource usage

 

Related Work
Brisaboa, Nieves R., Susana Ladra, and Gonzalo Navarro. "k2-trees for Compact Web Graph Representation." International symposium on string processing and information retrieval. 2009.
Claude, Francisco, and Gonzalo Navarro. "Fast and compact web graph representations." ACM Transactions on the Web (TWEB). 2010.
Dann, Jonas, Daniel Ritter, and Holger Fröning. "Demystifying Memory Access Patterns of FPGA-Based Graph Processing Accelerators." Proceedings of the 4th ACM SIGMOD Joint International Workshop on Graph Data Management Experiences & Systems (GRADES) and Network Data Analytics (NDA). 2021.
Yao, Pengcheng, Long Zheng, Xiaofei Liao, Hai Jin, and Bingsheng He. "An Efficient Graph Accelerator with Parallel Data Conflict Management." Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques. 2018.


ROLE REQUIREMENTS

 

  • Student (f/m/d) at a university or a university of applied sciences
  • Preferred fields of study: Computer science or electrical engineering
  • Prior experience in graph processing
  • Prior experience in FPGA programming (beneficial)
  • Strong system level programming skills (e.g., C / C++)

 

Your set of application documents should contain a cover letter, a resume in table form, school leaving certificates, certificate of enrollment, current university transcript of records, copies of any academic degrees already earned, and if available, references from former employers (including internships). Please also describe your experience and skills in foreign languages and computer programs / programming languages.
 

#Workingstudent #Werkstudent #Internship #Praktikum #Thesis #Germany #Deutschland #Student #HANADatabaseStudent

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Qualified applicants will receive consideration for employment without regard to their age, race, religion, national origin, ethnicity, age, gender (including pregnancy, childbirth, et al), sexual orientation, gender identity or expression, protected veteran status, or disability.

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 Requisition ID:311134 | Work Area: Software-Research | Expected Travel: 0 - 10% | Career Status: Student | Employment Type: Intern  | Additional Locations: 

Master Thesis Student (f/m/d) - In-line Graph Decompression for FPGA-based Graph Processing

Facility:  311134
Posted Date:  Dec 29, 2021
Work Area:  Software-Research
Career Status:  Student
Employment Type:  Intern
Expected Travel:  0 - 10%
Location: 

Walldorf, DE, 69190


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